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A distributed-parallel processing system joins multiple computers (or multiple CPU's) together into one system (or one machine) to achieve higher performance than a single computer (or a single CPU). In such a system, the number of computers (or CPU's) is changed according to performance requirements. A distributed-parallel processing system is called `scalable' if the system is able to cope with the change of the number of computers (or CPU's), i.e. the change of the scale.
There are two types of scalable system; one requires applications to be rewritten whenever the scale is changed, and the other just needs simple recompilation or reconfiguration. SSS-CORE is a scalable system of the latter type.
workstation cluster
A workstation cluster is a set of workstations connected with a high-speed network. It is also called a `network of workstations (NOW)'. A server cluster and a PC cluster are varieties of cluster system.
SSS-CORE -- origin of its name
T. Matsumoto, who is a general clerk and a chief architect and a chief programmer of SSS-CORE, proposed a synchronization scheme named `Snoopy Spin wait (SS-wait)' in 1989. SS-wait was designed to be implemented on a shared memory system and to be used for synchronization in a multitasking environment without a drop in performance. There was an operating system being developed on a shared memory parallel machine to support SS-wait. This operating system was called `SS-CORE'.
SSS-CORE is a successor to SS-CORE. This new OS expands its aim from a shared memory system to a workstation cluster or a distributed memory parallel machine. As the new OS aims at more scalable (i.e. easier to increase the number of machines) systems, it is called `Scalable SS-CORE', or `SSS-CORE' (pronounced `three ess core').
Ethernet / Fast Ethernet
Ethernet is a standardized network technology developed at Xerox. It is widely used for LAN (Local Area Network). Ethernet transmits data at a rate of 10 Mbps (i.e. 10,000,000 bits per second). Fast Ethernet transmits at a rate of 100 Mbps. The latest commercial Ethernet is Gigabit Ethernet, which transmits at a rate of 1 Gbps (i.e. 1,000,000,000 bits per second).
TCP/IP (Transmission Control Protocol / Internet Protocol)
TCP and IP are communication protocols for the Internet. They were designed at the Defense Advanced Research Projects Agency (DARPA). They have become the de facto standard both for the Internet and for LAN. Although TCP and IP are distinct protocols, they are often used together. Therefore they are called `TCP/IP' in a lump.
IPsec is a communication protocol based on IP. IPsec appends security of communication to IP. TCP/IP and UDP/IP gain security from IPsec without being aware of it.
IPsec provides encryption, integrity ensurance, and authentication of data. Encryption protects data from peeping even if the communication path is monitored. Encrypted data does not make sense to anyone but the intended party. Integrity ensurance means that modifications to data can be detected. Authentication verifies the identity of the origin of data.
Secure Sockets Layer (SSL) is another widespread mechanism for secure communication. SSL is implemented as a part of the user application, while IPsec is in the system program or the communication hardware. IPsec implementation is more likely to be high-speed, since it can cooperate closely with other system programs and the hardware.
Multiple computers are connected with a network in a distributed processing system (or a parallel processing system). Each computer of such a system is called a `node'.
In a centralized system, one host computer manages the whole system. In a distributed-parallel processing system, on the other hand, every node cooperates with each other to manage the system.
remote memory access
It facilitates programming for a parallel processing system if remote memories of the other computers can be accessed freely as well as a nearby memory of the local computer. An operation on a remote memory is called a `remote memory access'.
The functionality of a remote memory access is provided either by hardware or by software. SSS-CORE offers it by software, as MBCF, since SSS-CORE is intended to be used without dedicated hardware.
A cache is a mechanism to improve effective performance of a computer by reducing access time for slow storages (e.g. a main memory and a disk). When data is read from a slow storage, it is preserved in a fast storage (i.e. it is cached). When the same data is to be read again, the preserved data is used and the original slow storage is not accessed.
Effective performance of a distributed-parallel system is remarkably improved by caching data on the local node when remote memory accesses are performed. But not all copies of data are allowed to be cached simultaneously because the amount of the local fast storage is limited. When data is modified and the old data is copied in some cache, the copied data should be updated or invalidated.
A `cache read miss' means that the cache does not contain the data to be read.
Some distributed-parallel systems make it possible for their tasks to move, or migrate, from a node to another node while the tasks are running. This is called `task migration'. In such systems, tasks running on a heavily-loaded node may migrate to a lightly-loaded node to balance the loads across the system.
The `real' migration is very hard to implement on Windows or UNIX because their system call suites for communication are designed to keep on running on a single node throughout. SSS-CORE employs a virtualized communication mechanism of MBCF for interprocess communication to enable the `real' migration. The `real' migration means that a migrated task can continue to run even after the original node is shut down. SSS-CORE is equipped with the `real' migration so that it is possible to increase or decrease nodes while applications are running.
official mascot `Manekikko'
`Manekikko' is designed as an official mascot for SSS-CORE, as well as the Linux Penguin and the BSD Daemon.
Ms. Hiroko Satoh @ RIKEN suggested us for using a Japanesque lucky cat `manekineko' as a motif. Ms. Miki Umezawa @ Tama Art University designed the character under the guidance of Ms. Fusako Kusunoki.

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